Posted By: Anonymous
Can I pass variables to a GNU Makefile as command line arguments? In other words, I want to pass some arguments which will eventually become variables in the Makefile.
You have several options to set up variables from outside your makefile:
From environment – each environment variable is transformed into a makefile variable with the same name and value.
You may also want to set
--environments-override) on, and your environment variables will override assignments made into makefile (unless these assignments themselves use the
overridedirective . However, it’s not recommended, and it’s much better and flexible to use
?=assignment (the conditional variable assignment operator, it only has an effect if the variable is not yet defined):
Note that certain variables are not inherited from environment:
MAKEis gotten from name of the script
SHELLis either set within a makefile, or defaults to
/bin/sh(rationale: commands are specified within the makefile, and they’re shell-specific).
From command line –
makecan take variable assignments as part of his command line, mingled with targets:
make target FOO=bar
But then all assignments to
FOOvariable within the makefile will be ignored unless you use the
overridedirective in assignment. (The effect is the same as with
-eoption for environment variables).
Exporting from the parent Make – if you call Make from a Makefile, you usually shouldn’t explicitly write variable assignments like this:
# Don't do this! target: $(MAKE) -C target CC=$(CC) CFLAGS=$(CFLAGS)
Instead, better solution might be to export these variables. Exporting a variable makes it into the environment of every shell invocation, and Make calls from these commands pick these environment variable as specified above.
# Do like this CFLAGS=-g export CFLAGS target: $(MAKE) -C target
You can also export all variables by using